Senior Researcher Tero Säntti

A brief history of my more practical electronics projects

This is not a complete list, but it covers the most interesting steps on the way.

Early days and home projects

This is just a list of some of the old electronics projects I have done. The order should be correct, but the actual time might be off by a year or two...

• 1981: My first LED blinker circuit. The basic design with 2 transistors, 2 LEDs, 2 capacitors, 2 resistors and 2 variable resistors.
• 1986: A digital door bell. Contained a ROM with 24 tunes, selector circuit and a few adjusts (speed, pitch and volume, if I remember correctly).
• 1989: A solder on the motherboard memory extension for my Amiga500. This one was a scary project.
• 1990: A pair of speakers. Actual electronis limited to the audio crossover... Anyway the design of the crossover as well as the box shape and size required some study of audio electronics and acoustics.
• 1995: A Lego car. Simple Lego built car with two Microchip PIC16F84 microcontrollers, one driving the rear wheels and one "navigating" and steering. For steering and propulsion I used stepper motors from two old matrix printers I dismantled. The "navigation" was based on a few feelers/whiskers made out of paper clips.
• 1996: A stereo amplifier. A small audio amplifier with volume, balance, bass and trebble controls. Selectable output for either speakers or headphones. All built inside a 5 1/4 drive bay of a PC.
• 1997: A harddrive controller for Amiga500. Connected via a flat cable soldered on the motherboard. The hardware worked just fine, but my assembler language device driver had some bug, since the drive always appeared empty after power up. As long as the power was applied, it worked fine. Never got around to find the bug :-(
• 1998: A Video "repairer". An analog circuit for restoring lost sync signals and inverting polarity of the brightness. Remote control via JVC Compulink from my stereo connected to a PIC cannibalized from the Lego car.
• 1999: An analog filter with very long time constant. A simple low pass filter with time constant of more than two minutes and three operatig modes (bypass, run and set). Problematic due to the leaks in the high capasity condensator. This was designed for use in radiation physics laboratory, operated by students, so the design was short circuit protected on all ports. (Note, apparently this system is still being used in the spring of 2013!)

FPGA related practical projects

• 1998: First contact with FPGAs. Some very simple projects for a course on HDL based circuit design. The board might have been based on Xilinx 4000 series, not sure any more...
• 2005: First encounter with XESS 3S1000 and XST3 combination. Started with some tests for the board, displaying an image on a monitor, some image filtering, cache memory for the filter, hard drive control and so on. Finally implemented the first version of REALJava on this board. (further details about the progress of REALJava below) This board is based on a Spartan3 1000 chip.
• 2006: I got access to a ML310 board. As always, some demonstrations, both standalone and with an operating system (Linux). After some poking around I managed to implement a REALJava core on the system, with the software partition running on the hardcore PPC405, making it the first "fast" implementation. This board housed a Virtex2Pro30 FPGA chip with dual PPC405 cores.
• 2007: We obtained a ML410 board. With a relatively short learning period (the board is very much like the ML310) I ported the hardware to the new board. The main benefit being larger FPGA size, allowing up to 3 REALJava cores to be implemented in the system. The board was a step up to a new generation of FPGAs, namely the Virtex4FX60, also with dual PPC405s.
• 2008: Realtime video. Used the XESS boards to capture live television stream and send it to a monitor. Had a hard time finding monitors accepting this low sync rates (50hz for PAL video). This has been used as the starting point for student projects performing various filtering and overlay functions.
• 2009: Virtex5 era begins. We acquired a new larger (based on the amount of the FPGA logic) board from Avnet, namely AES-XLX-V5LXT-PCIE110-G with a Virtex5LX110T chip. The chip no longer contains hardcore PPCs, so a MicroBlaze softcore CPU was used instead. So far up to 8 parallel REALJava cores have been implemented on this system.
• 2010: Partial reconfiguration. The first attempts at PR, and after some playing around, a fully functional system with a runtime reconfigurable REALJava core available.
• 2010: PIC16 series CPU on several FPGA platforms. Implemented a PIC16C5X compatible CPU on the XESS, Avnet and ML605 boards. Compatible with the Microchip assembler compiler.
• 2011: FPGA for the LET. Control, communication and analysis for the LET instrument, a part of the Solar Orbiter satellite project. Current prototype is fully functional save for the analysis part. Implemented with Actel AP250, APE1500 and APE3000, the last is a prototyping emulator for RTAX2000SL from Aldec.
• 2011: FPGA emulator of the PHASIC chip. Implemented on XESS 3S1000, used for developing control for the PHASIC. Three PHASICs are used for one LET unit.
• 2012: SOLOJava, a standalone version of the REALJava co-procesor core. Initially implemented on the XESS board, and then on a Virtex5 board. Some preliminary performance figures are available at the REALJava result site.
• 2013: FPGA interface to the Kovilta KOVA1 vision chip. Performance and stability improvements, maximum frame rate upto 10 000 fps for BW images and around 2 000 fps for gray scale images (~3x improvement), using a Spartan6.
• 2014: Implementing a Hough transform for lines on the FPGA connected to the Kovilta KOVA1 vision chip. Initial purpose was to enable seam tracking during high power (10kW) laser welding. Maximum frame rate for the transform is around 2 000 fps, depending on image data. The transform unit does not interfere with the normal operation of the camera.
• 2015: Implementing automatic capture of the laser center point, distance between the seam and the laser center point, and mode filter for cleaning up the distance data. The mode filter is "ultra fast" approximation, and only takes 4 clk cycles even though the search space is 8 bits wide. The output could be used to control the welding robot directly.
• 2016: FPGA-based camera. A setup with 20+ Mpixels, all prosessing done on FPGA, including ethernet for communication. The processing steps include de-bayer, black level calibration, whitebalance correction, optional sharpness enhacement and JPG compression. Data rate is quite high, as the camera chip supports upto 10 parallel channels from the chip to the FPGA, each running over 550Mbits / sec resulting in aggregate bandwidth of over 5.5 Gbits per sec.
• 2017: FPGA-based emulator for voltage and frequency scaling, 32 bit cpu + DSP core, software controllable frequency and emulated voltage levels, timing information generated from voltage-frequency combination on-the-fly with hardware, used for SW development and design verification while the actual chips are being manufactured. Debug data pushed to a monitor via HDMI and/or VGA in real time, including all the frequencies and voltages (real and emulated) and register values for the emulated on board chips that will provide the functionality on the real PCB.
• 2017: FPGA-based control system for an experimental camera, controls the experimental camera chip and on board bias sources, includes a minimal custom instruction set processor to execute sequences on the camera chip and also memories for the images and the instruction streams.
• 2018: Communication models for two cubesat instruments, both based on the same MicroSemi APE3000L, so I integrated the two in to one commercial FGPA prototyping board. A dip switch is used to select which instrument's protocol is used. The instruments are XFM-CS and PaTe-Foresail. Later the XFM-CS side continued to be developed, incrementally, to support instrument level testing.
• 2019: Complete FPGA design for XFM-CS instrument, including communication protocol, housekeeping data, scientific data analysis pipeline, result storage and buffering, SEU hardening of memories and selected registers, calibration and development support functions. Initial testing shows performance to be inside design targets while power consumption is below the allocated limit.
• 2019: Almost complete FPGA design for the Foresail-1 / PaTe instrument, including communication protocol, housekeeping data, scientific data acquisition, result storage and buffering, SEU hardening of memories and selected registers, calibration and development support functions. The scientific data analysis (particle detection after data acquisition and before spectrum collection) has been done by others.
• 2019: FPGA-based control system for an experimental camera, controls the experimental camera chip and on board bias sources, includes a minimal custom instruction set processor to execute sequences on the camera chip and also memories for the images and the instruction streams. Also a second prototype using two separate FPGA platforms, one for execution and one for communication with the PC. Note, this is not the same as in 2017, new camera chip with new controls was used.
• 2020: FPGA design for a miniature microscope, controls an image sensor and peripherals, including data streaming and link to secondary support FPGA that handles communication to PC. Later versions will include stepper motor control to move the sample, non-volatile storage and autonomous operation. The autonomous operation is the rationale behind the support FPGA system. It allows minimal size for the actual microscope device. Think of a pack of cigarettes, a bit wider in the smallest dimension, and a bit smaller in the others. Both devices use Xilinx Artix-7 FPGAs.
• 2021: Two RISC-V implementations on FPGAs. The first used VexRiscv on Xilinx Artix-7, and the second used NEORV32 on Xilinx Kintex UltraScale. The NEORV32 was very easy to adopt, and took less than a day from initial download to executing own code on real hardware.
• 2021: High speed LVDS communication tester, multiple lanes, 800Mbit/sec per lane, automatic eye diagram centering, byte alignment and output buffering all running directly on hardware. Preliminary test version running at slower speed on Xilinx Artix-7, and the full speed version running on Xilinx Kintex UltraScale. Included (pseudo)random data generator used to create test data at live speed.
• 2022: Ultra high speed communication between FPGAs, with 4 wires the speed achieved was more than 4Gbit/sec per direction. Both directions were active at the same time (full duplex). With 8 wires the total bandwidth was 16.5Gbit/sec (aggregate of both directions). The actual line rates are a bit higher, the values here are the user payload tranfers. The FPGAs would reach even higher speeds, but the PCBs and 6 inch wires were not specifically tailored for this, and that limited the performance. Tested with running 5 Tera bits of (pseudo)random data over the links, with no errors detected. Two Xilinx Kintex UltraScale FPGAs were used in this.
• 2022: First prototype of the MIRA instrument, ultra low cost miniture radiation detector planned to go on board Aalto-3 satellite. Small and cheap components, testing of their longevity under harsh conditions. Also targets scientific goals with a novel, simplified sensor + readout electronics, with relatively low sampling frequency.
• 2022: Two FPGA system for reading 373 magnetic sensors, each producing 3D data, and calculating the centerpoints from the data. Maximum frame rate achieved from the sensor array to PC (with processign split between the two FPGAs) is over 400 frames per second. Improved accuracy, latency and time code labeling compared to the microcontroller + FPGA solution used before. Allows additional inputs and fuctions to be analysed at temporal resolution of 1 microsecond, fully synchronized with the magnetic data stream. Multiple communication schemes used to move all of the data and commands.
• 2022: Ultra high speed communication with better quality physical connection, top speed now extended to 10Gbit/sec per direction over just one pair of wires for each direction. With maximum of 4 pairs per direction, the aggregate bandwith would be 80Gbit/sec. This used heterogenous FPGAs, one UltraScale and one UltraScale+, both from Xilinx.
• 2023: FPGA for XFM instrument. Similar principles as XFM-CS, but two detector channels, and communication over SpaceWire. The FPGA was upgraded to RTG4, providing much better radition tolerance. Changes in operation logic made the instrument more autonomous during normal operation and the standard data interface allows easier integration to different host satellites. Initial testing shows all goals are met while staying inside the allocated budgets.