Research
Java Related This line of research was started around
2004, and focuses on creting a hardware accelerated Java virtual
machine for embedded systems. This research was a part of the REALJava
project, and more recently has been continued in the VirtuES
project. My Ph.D. thesis was on
this topic. Currently the focus is on multicore implementation, and we
now have a system running up to 8 REALJava cores in parallel. The
number of cores is limited by the amount of FPGA logic available, and
with a larger chip it could be easily increased. The architecture
poses no limits on the number of cores.
Later a standalone version has been made. It requires no CPU, but has
some limitations. The biggest one is, that it does not support dynamic
class loading. All of the required classes need to be preloaded to the
FPGA in advance.
Dynamic Reconfiguration The research on dynamic
reconfiguration has just been staretd, and currently only a technology
demonstration has been actually implemented. The implementation
started with an existing design running on a Virtex5LX110T chip. The
chip is populated on a a board from Avnet
(AES-XLX-V5LXT-PCIE110-G). The basic design contains a MicroBlaze CPU
running Linux as the operating system, 1-8 REALJava cores, and of
course all the support modules (PLB4.6, DDR2, Ethernet etc.). This
design comes from the VirtuES project. As the first step all of the
REALJava cores were removed, and just a simple reconfigurable module
was added to the PLB bus. The main reason for this version was
ensuring correct operation before, during and after
reconfiguration. Especially the bus inteface was under scrutiny. Also
the software responsible for actually loading the partial bitstreams
to the FPGA was prototyped with this version of the design. After a
few attempts, all went well and the final design was extented to
include a full size REALJava core as a reconfigurable module. The
functionality of the system was the verified by running the REALJava
virtual machine, which showed exactly the same performance
characteristics as in the static reference design. The software runs
as a normal user mode executable on top of the operating system, and
it can fetch the bitstreams from any mounted data source. At the
moment an NFS connection is used as the main data storage, and the
bitstreams are stored there.
Space Applications In the past there has been a few small
scale projects related mainly to prototyping space hardware using
FPGAs. Nowadays there is a growing interest in the use of
reconfigurable hardware for actual payloads as well as the
prototypes. Various architectures (SRAM, Antifuse, FLASH) are being
compared based on flexibility, radiation tolerance and required data
protection mechanisms (TMR, scrubbing etc.). Additionally the use of
dynamic reconfiguration during flight is of great interest.
I am also a supervisor in the RadMon project, aiming to build a radiation
detector for the Aalto-1 satellite. The whole satellite is student driven,
and so is the RadMon. One of the most interesting scientific aspects of the
RadMon is that it is the first instrument in it's class to use fully
digital processing. Normally comparable instruments perform heavy analog
processing, but in this case it has been moved to the digital domain,
inside an FPGA. The instrument is currently flying, and it is working correctly.
Around 2011 - 2013 I was involved in developing the LET (Low Energy Telescope)
instrument, a part of the EPD
(Energetic Particle Detector) cluster for the
Solar Orbiter
satellite. I focused on FPGA topics, including
device selection, specification, implementation, prototyping, testing and documentation.
The prototypes were implemented using Actel FPGAs, and the final
device was selected to be RTAX2000SL. The FPGA handles housekeeping, control, communication
and scientific on-board analysis of the data for the instrument.
I have also been working on embedded software for a device that was operated in the ISS.
My responsibilities in that project were designing the database structures for the
whole system, collecting and compressing data for downlink, decompressing and
processing uplinked commands and files, and setting up an EGSE for testing and
SW development. All of the transactions between the unit ant the EGSE are secure,
and they are also verified with a MD5 check sum. The system runs Linux on a PPC405,
and the EGSE runs on php in a browser. Both Windows and Linux versions have been tested,
but getting it to work in Windows requires a lot of third party helper programs.
These include normal *nix commanline tools, like tar, gzip and md5. All are
readily availble for Windows, but getting it all to work is a bit of a hassle.
The system was succesfully operating in the ISS.
Since 2017 I have been developing FPGAs for a few cubesat projects. Most important ones have been XFM-CS and Foresail-1/PaTe. Both of these are radiation mesurement instruments, XFM-CS analyzes X-ray spectrum at two different temporal resolutions while PaTe is a particle detector (electrons and protons) with two telescopes. Both use MicroSemi FPGAs, namely A3PE3000L.
Imaging, Image Processing and Computer Vision Currently
I am working on a project focusing on monitoring and controlling high
power laser welding of thick steel. My contributions in this project
are on the hardware side of things, more specifically in the FPGA
development. As a part of this project I have improved the FPGA
controlling the Kova 1 vision chip. The FPGA is now upto 3 times faster
and some stability related issues have been solved also. Additionally
the FPGA can now perform a Hough transform for finding lines in the image.
This unit can even fine tune some of the bias voltages on the vision chip,
in order to improve the quality of the input images. The purpose of the
transform is to find the seam between the steel plates to be welded, and
make sure that the laser hits the middle of the seam.
My other project in the imaging field is a software project, which focuses
on detecting space debris from telescope images. In this project my
involvement has been mainly on testing and developing methods for
performing prototype runs on large data sets to measure the performance of
the software. This has included a lot work with databases containing data
on the input images, their qualities, the objects to be found on the images
and so on. The outputs are also gathered in databases, so that he results of
different versions can be compared. Various analysis tools have been developed
to pinpoint possible deficiencies. Additionally I have participated in the
development of the detection software and its implementation in C++.
I also participated in the Marin2
project. The project focuses on applying augmented reality tecniques to
industrial applications. AR related research will be done in the fields
of user experience, visual tracking, hardware acceleration and data integration.
I have also designed FPGA-based control, communication and data acquisition
systems for various cameras, including both commercial and experimental image
sensors. The challenges have varied widely, covering issues from timing of
individual signals (>500MHz on PCB) to throuput issues (>5Gbit/sec) and
fine tuning of analog voltages (bias levels). Also bandwidth issues in
communication over USB (2 and 3), ethernet (100M and 1G), and even serial
links (~100kbit -> few Mbits per sec) have been limiting factors.
Something to think about"I believe in evidence. I believe in observation, measurement, and reasoning,
confirmed by independent observers. I'll believe anything, no matter how wild
and ridiculous, if there is evidence for it. The wilder and more ridiculous
something is, however, the firmer and more solid the evidence will have to be."
Isaac Asimov, The Roving Mind
"In science one tries to tell people, in such a way as to be understood by everyone,
something that no one ever knew before. But in poetry, it's the exact opposite."
Paul Dirac
|
