This line of research was started around
2004, and focuses on creting a hardware accelerated Java virtual
machine for embedded systems. This research was a part of the REALJava
project, and more recently has been continued in the VirtuES
project. My Ph.D. thesis was on
this topic. Currently the focus is on multicore implementation, and we
now have a system running up to 8 REALJava cores in parallel. The
number of cores is limited by the amount of FPGA logic available, and
with a larger chip it could be easily increased. The architecture
poses no limits on the number of cores.
The research on dynamic reconfiguration has just been staretd, and currently only a technology demonstration has been actually implemented. The implementation started with an existing design running on a Virtex5LX110T chip. The chip is populated on a a board from Avnet (AES-XLX-V5LXT-PCIE110-G). The basic design contains a MicroBlaze CPU running Linux as the operating system, 1-8 REALJava cores, and of course all the support modules (PLB4.6, DDR2, Ethernet etc.). This design comes from the VirtuES project. As the first step all of the REALJava cores were removed, and just a simple reconfigurable module was added to the PLB bus. The main reason for this version was ensuring correct operation before, during and after reconfiguration. Especially the bus inteface was under scrutiny. Also the software responsible for actually loading the partial bitstreams to the FPGA was prototyped with this version of the design. After a few attempts, all went well and the final design was extented to include a full size REALJava core as a reconfigurable module. The functionality of the system was the verified by running the REALJava virtual machine, which showed exactly the same performance characteristics as in the static reference design. The software runs as a normal user mode executable on top of the operating system, and it can fetch the bitstreams from any mounted data source. At the moment an NFS connection is used as the main data storage, and the bitstreams are stored there.
In the past there has been a few small
scale projects related mainly to prototyping space hardware using
FPGAs. Nowadays there is a growing interest in the use of
reconfigurable hardware for actual payloads as well as the
prototypes. Various architectures (SRAM, Antifuse, FLASH) are being
compared based on flexibility, radiation tolerance and required data
protection mechanisms (TMR, scrubbing etc.). Additionally the use of
dynamic reconfiguration during flight is of great interest.
Imaging, Image Processing and Computer Vision
I am working on a project focusing on monitoring and controlling high
power laser welding of thick steel. My contributions in this project
are on the hardware side of things, more specifically in the FPGA
development. As a part of this project I have improved the FPGA
controlling the Kova 1 vision chip. The FPGA is now upto 3 times faster
and some stability related issues have been solved also. Additionally
the FPGA can now perform a Hough transform for finding lines in the image.
This unit can even fine tune some of the bias voltages on the vision chip,
in order to improve the quality of the input images. The purpose of the
transform is to find the seam between the steel plates to be welded, and
make sure that the laser hits the middle of the seam.
Something to think about
"I believe in evidence. I believe in observation, measurement, and reasoning,
confirmed by independent observers. I'll believe anything, no matter how wild
and ridiculous, if there is evidence for it. The wilder and more ridiculous
something is, however, the firmer and more solid the evidence will have to be."
|Last updated: October 06 2017 23:50:31.|